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mb9b120m series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf124k/l/m, MB9BF122K/l/m, mb9 bf121k/l/m data sheet (full production) publication number mb9b120m_ds706 - 00050 revision 3.0 issue date march 1 8 , 201 5 confidential notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this docum ent are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur . d a t a s h e e t mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential notice on data sheet designations spansion inc. issues data sheets with advance information or preliminary de signations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that th ey have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicate s that spansion inc. is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following conditions upon advance information content: this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not d esign in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice. preliminary the preliminary designation indicates that the product development has progressed suc h that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full product ion is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of th e manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. combination some data sheets contain a combination of products with d ifferent designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc ch aracteristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of t ime such that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a spee d option, temperature range, package type, or vio range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion inc. applies the following conditions to documents in this cate gory: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expect ed to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. questions regarding these document designations may be directed to your local sales office . mb9b120m series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf124k/l/m, MB9BF122K/l/m, mb9bf121k/l/m data sheet (ful l production) publication number mb9b120m_ds706 - 00050 revision 3.0 issue date march 1 8 , 201 5 confidential this document states the current technical specifications regarding the spansion product(s) described herein. span sion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. ? description the mb9 b 1 20m series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with low - power consumption mode and competitive cost . th ese s eries are based on t he arm cortex - m3 processor with on - chip flash memory and sram , and have peripheral functions such as various t imers , adcs , dac s and communication interfaces (uart , c sio , i 2 c , lin ). the products which are described in this data sheet are placed into type 9 product categories in "fm3 family peripheral manual". note : arm and cortex are the r egistered trademarks of arm limited in the eu and other countries. d a t a s h e e t 2 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? features ? 32 - bit arm cortex - m3 core ? processor version : r2p1 ? up to 72 mhz frequency operation ? integrated nested vectored interrupt controller (nvic) : 1 nmi (non - maskable interrupt ) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick) : system timer for os task management ? on - chip memories [flash memory] ? dual operation flash memory ? dual operation flash memory has the upper bank and the lower bank. so, this series could implement erase, write and read operations for each bank simultaneously. ? main area: up to 256 k byte s (up to 240 kbytes upper bank + 16 kbytes lower bank) ? work area: 32 kbyte s (lower bank) ? read cycle: 0 wait - cycle ? security function for co de protection [sram] this series on - chip sram is composed of two independent sram (sram0 , sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0 : up to 16 kbyte s ? sram1 : up to 16 kbyte s ? multi - f unction s erial i nterface (max eight channels ) ? 4 channels with 16 steps9 - bit fifo (ch. 0/1/3/4 ) , 4 channels without fifo (ch. 2/5/6/7 ) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c [uart] ? full duplex double buffer ? selec tion with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically control the tran smission /reception by cts/rts (only ch.4) ? various error detection functions availa ble (parity errors , framing errors , and overrun errors) [csio] ? full duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function available [lin] ? lin protocol rev.2.1 supported ? full duplex double buffer ? master/slave mode supp orted ? lin break field generation (can be changed to 13 to 16 - bit length) ? lin break delimiter generation (can be changed to 1 to 4 - bit length) ? various error detection functions available (parity errors , framing errors , and overrun errors) [ i 2 c] standard mo de (max 100 kbps) / fast mode (max 400 k bps) supported d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 3 confidential ? dma controller ( eight channels) the dma controller has an independent bus from the cpu , so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfe r can be started by software or request from the built - in peripherals ? transfer address area : 32 - bit (4 gbyte s ) ? transfer mode : block transfer/burst transfer/demand transfer ? transfer data type : byte/half - word/word ? transfer block count : 1 to 16 ? number of tra nsfers : 1 to 65536 ? a/d converter (max 26 channels) [ 12 - bit a/d converter ] ? successive approximation type ? built - in 2 unit s ? conversion time : 0.8 s @ 5 v ? priority conversion available (priority at 2 levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion : 16 steps , for priority conversion : 4 steps) ? d/a converter (max two channels) ? r - 2r type ? 10 - bit resoluti on ? base timer (max eight channels) operation mode is selectable from the followings for each channel . ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer ? general - purpose i/o port this series can use its pins as general - purpos e i/o ports when they are not used for peripherals. moreover , the port relocate function is built in . it can set which i/o port the peripheral function can be allocated to . ? capable of pull - up control per pin ? capable of reading pin level directly ? built - in t he port relocate function ? up to 65 high - speed general - purpose i/o ports @ 80 pin package ? some ports are 5 v tolerant. s ee " ? list of pin functions " and " ? i/o circuit type " to confirm the corresponding pins ? dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each channel . ? free - running ? periodic (=reload) ? one - shot d a t a s h e e t 4 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? quadrature position/ revolution counter (qprc) ( max tw o channels ) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use as the up/down counter. ? the detection edge of the three external event input pins ain , bin and zin is co nfigurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers ? multi - function t imer the multi - function timer is composed of the following blocks. ? 16 - bit free - run timer 3ch . /unit ? input capture 4 ch . /unit ? output compare 6ch . /unit ? a/d activati on compare 2 ch . /unit ? waveform generator 3ch . /unit ? 16 - bit ppg timer 3ch . /unit the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input c apture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function ? real - time clock (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 01 to 99. ? the interrupt function with specifying da te and time (year/month/day/hour/minute/second/a day of the week.) is available. this function is also available by specifying only year, month, day, hour or minute. ? timer interrupt function after set time or each set time . ? capable of rewriting the time wi th continuing the time count. ? leap year automatic count is available. ? watch counter the watch counter is used for wake up from s leep and t imer mode. interval timer : up to 64s (max) @ sub clock : 32.768 khz ? external interrupt controller unit ? up to 23 ex ternal interrupt input pin s @ 80 pin package ? include one non - maskable interrupt (nmi) input pin ? watchdog t imer ( two channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watc hdogs , a " hardware " watchdog and a " software " watchdog. the " hardware " watchdog timer is clocked by the built - in l ow - speed cr oscillator. therefore , the " hardware" watchdog is active in any low - power consumption modes except rtc, s top , deep s tandby rt c, deep s tandby s top modes . d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 5 confidential ? crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. c citt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial : 0x1021 ? ieee - 802.3 crc32 generator polynomial : 0x04c11db7 ? clock and reset [clocks] selectable from five clock sources (2 external oscillator s , 2 built - in cr oscillator s , and main pll). ? main clock : 4 mhz to 48 mhz ? sub clock : 32.768 khz ? built - in h igh - speed cr clock : 4 mhz ? built - in l ow - speed cr clock : 100 khz ? main pll clock [resets] ? reset requests from initx pin ? power - on reset ? software reset ? w atchdog timers reset ? low - voltage detection reset ? c lock super visor reset ? clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? if external clock failure (clock stop) is detected , reset is asserted. ? if ex ternal frequency anomaly is detected , interrupt or reset is asserted. ? low - voltage detector (lvd) this series include s 2 - stage monitoring of voltage on the vcc pins . when the voltage falls below the voltage that has been set , low - voltage detector generates an interrupt or reset. ? lvd1 : error reporting via interrupt ? lvd2 : auto - reset operation ? low - power consumption m ode six low - power consumption modes supported. ? s leep ? t imer ? rtc ? s top ? deep s tandby rtc ( selectable between k eeping t he value of ram and not ) ? deep s tandby s top (selectable between k eeping the value of ram and not) ? debug seria l wire jtag debug port (swj - dp) ? unique id unique value of the device ( 41 bits ) is set. ? power supply wide range voltage : vcc = 2.7 v to 5.5 v d a t a s h e e t 6 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? pro duct lineup ? memory size product name mb9 b f 1 2 1 k / l / m mb9 bf 1 22k/l/m mb9 bf 1 24k/l/m on - chip flash memory main area 64 kbytes 128 kbytes 256 kbytes work area 32 kbytes 32 kbytes 32 kbytes on - chip s ram sram0 8 kbytes 8 kbytes 16 kbytes sram1 8 kbytes 8 kbyt es 16 kbytes total 16 kbytes 16 kbytes 32 kbytes ? function product name mb9bf 1 21k mb9bf 1 22k mb9 bf 1 24k mb9bf 1 21l mb9bf 1 22l mb9 bf 1 24l mb9bf 1 21m mb9bf 1 22m mb9 bf 1 24m pin count 48 64 80 /96 cpu cortex - m3 freq. 72 mhz power supply voltage range 2.7 v to 5.5 v dmac 8ch . multi - function serial interface (uart/csio /lin /i 2 c) 4 ch. (max) ch.0/1/3 : fifo ch.5 : no fifo (in ch. 1/ 5 , only uart and lin are available.) 8 ch. (max) ch .0/1/3/4 fifo ch .2/5/6/7 : no fifo (in ch. 1 , only uart and lin are available.) base tim er (pwc/reload timer/pwm/ppg) 8 ch . (max) mf - timer a/d activation compare 2 ch. 1 unit input capture 4ch.* free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 1 ch . 2 ch . (max) dual timer 1 unit real - time clock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 14 pins (max) + nmi 1 1 9 pins (max) + nmi 1 23 pins (max) + nmi 1 i/o ports 35 pins (max) 50 pins (max) 65 pins (max) 12 - bit a/d converter 1 4 ch . (2 unit s ) 23 ch . (2 unit s ) 2 6 ch . (2 unit s ) 10 - bit d/a converter 2ch . (max) csv (clock super visor) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp unique id yes *: t he external input c hannel which can be used is shown as follws. ? ch.0 to ch.3 : mb9bf121m/f122m/f124m ? ch.0, ch.2, ch.3 : mb9bf121k/f122k/f124k, mb9bf121l/f122l/f124l d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 7 confidential note : all signals of the peripheral function in each product cannot be allocated by limiting the pins o f package. it is necessary to use the port relocate function of the i/o port according to your function use. see " ? electrical characteristics 4.ac characteristics (3)built - in cr oscillation characteristics " for accuracy of buil t - in cr . d a t a s h e e t 8 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? packages product name package mb9b f12 1k mb9bf 12 2k mb9bf 12 4k mb9bf 12 1l mb9bf 12 2l mb9bf 12 4l mb9bf 121 m mb9bf 122 m mb9bf 124 m lqfp: fpt - 48 p - m 49 (0.5 mm pitch) ? - - qfn : lcc - 48 p - m 73 (0. 5 mm pitch) ? - - lqfp : fpt - 64p - m 38 (0.5 mm pitch) - ? - ? lqfp: fpt - 64 p - m3 9 (0. 6 5 mm pitch) - ? - qfn : lcc - 64 p - m 24 (0.5 mm pitch) - ? ? - lqfp: fpt - 80 p - m 37 (0.5 mm pitch) - ? - ? lqfp : fpt - 8 0p - m 40 (0.65 mm pitch) - ? - ? bga: bg a - 96 p - m0 7 (0. 5 mm pitch) - ? - ? ? : supported note : see " ? package d imensions " for detailed information on each package. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 9 confidential ? pin assignment ? fpt - 80p - m37/m40 (top view) d a t a s h e e t 10 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? fpt - 64 p - m3 8/m39 (top view) d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 11 confidential ? lcc - 64 p - m 24 (top view) d a t a s h e e t 12 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? fpt - 48 p - m 49 (top view) d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 13 confidential ? lcc - 48p - m73 (top view) d a t a s h e e t 14 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? bga - 96p - m07 (top view) d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 15 confidential ? list of pin functions ? list of pin numbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qf p - 64 qfn - 64 l qfp - 48 qfn - 48 1 b1 1 1 vcc - 2 c1 2 2 p50 f n int00_0 ain0_2 sin3_1 an22 3 c2 3 3 p51 f n int01_0 bin0_2 sot3_1 (sda3_1) an23 4 b3 4 4 p52 f n int02_0 zin0_2 sck 3_1 (scl3_1) an24 5 d1 - - p53 e l sin6_0 tioa1_2 int07_2 6 d2 - - p54 e l sot6_0 (sda6_0) tiob1_2 int18_1 7 d3 - - p55 e l sck6_0 (scl6_0) adtg _ 1 int19_1 8 e1 - - p56 e l int 08_2 9 e2 5 - p30 f n ain0_0 tiob0_1 int03_2 an25 d a t a s h e e t 16 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qfp - 48 qfn - 48 10 e3 6 - p31 f n bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 an26 11 g1 7 - p32 e l zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 12 g2 8 - p33 e l int04_0 tiob3_1 sin6_1 adtg_6 13 g3 9 5 p39 e l dtti0x_0 int06_0 adtg_2 14 h1 10 6 p3a g l rto00_0 (ppg00_0) tioa0_1 int07_0 subout_2 rtcco_2 15 h2 11 7 p3b g k rto01_0 (ppg00_0) tioa1_1 16 h3 12 8 p3c g l rto02_0 (ppg02_0) tioa2_1 int18_2 17 j1 13 9 p3d g k rto03_0 (ppg02_0) tioa3_1 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 17 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qfp - 48 qfn - 48 18 j2 14 10 p3e g l rto04_0 (ppg04_0) tioa4_1 int19_2 19 j4 15 11 p3f g k rto05_0 (pp g04_0) tioa5_1 20 l1 16 12 vss - 21 l5 - - p44 g l tioa4_0 int10_0 22 k5 - - p45 g l tioa5_0 int11_0 23 l2 17 13 c - 24 l4 - - vss - 25 k1 18 14 vcc - 26 l3 19 15 p46 d f x0a 27 k3 20 16 p47 d g x1a 28 k4 21 17 initx b c 29 j5 - - p48 e l int14_1 sin3_2 30 k6 22 18 p49 l l tiob0_0 int20_1 da0_0 - sot3_2 (sda3_2) ain0_1 31 j6 23 19 p4a l l tiob1_0 int21_1 da1_0 - sck3_2 (scl 3_2) bin0_1 d a t a s h e e t 18 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qfp - 48 qfn - 48 32 l7 24 - p4b e l tiob2_0 int22_1 igtrg_0 zin0_1 33 k7 25 - p4c i* l tiob3_0 sck7_1 (scl7_1 ) int12_0 ain1_2 34 j7 26 - p4d i* l tiob4_0 sot7_1 (sda7_1) int13_0 bin1_2 35 k8 27 - p4e i* l tiob5_0 int06_2 sin7_1 zin1_2 36 k9 28 20 md1 c e pe0 37 l8 29 21 md0 k d 38 l9 30 22 x0 a a pe2 39 l10 31 23 x1 a b pe3 40 l11 32 24 vss - 41 k11 33 - vcc - 42 j11 34 25 p10 f m an00 43 j10 35 26 p11 f n an01 sin1_1 int02_1 frck0_2 wkup1 44 j8 36 27 p12 f m an02 sot1_1 (sda1_1) ic00_2 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 19 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qfp - 48 qfn - 48 45 h10 37 28 avss - 46 h9 38 29 p14 f n an04 int03_1 ic02_2 sin0_1 47 g10 39 30 p15 f n an05 ic03_2 sot0_1 (sda0_1) int14_0 48 g9 - - p16 f n an06 sck0_1 (scl0_1) int15_0 49 f10 40 - p17 f n an07 sin2_2 int04_1 50 h11 41 31 avcc - 51 f11 42 32 avrh - 52 g11 43 33 av r l - 53 f9 44 - p18 f m an08 sot2_2 (sda2_2) 54 e11 45 - p19 f m an09 sck2_2 (scl2_2) 55 e10 - - p1a f n an10 sin4_1 int05_1 ic00_1 d a t a s h e e t 20 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qfp - 48 qfn - 48 56 e9 - - p1b f n an11 sot4_1 (sda4_1) ic01_1 int20_2 57 d10 46 34 p23 f m sck0_0 (scl0_0) tioa7_1 an12 58 d9 47 35 p22 f m sot0_0 (sda0_0) tiob7_1 a n13 - - zin1_1 59 c11 48 36 p21 f n sin0_0 int06_1 wkup2 bin1_1 an14 60 c10 - - p20 e n int05_0 crout _0 ain1_1 61 a10 49 37 p00 e j trstx 62 b9 50 38 p01 e j tck swclk 63 b11 51 39 p02 e j tdi 64 a9 52 40 p03 e j tms swdio 65 b8 53 41 p04 e j tdo swo 66 a8 - - p07 e l adtg_0 int23_1 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 21 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qf p - 48 qfn - 48 67 c8 54 - p0a j* n sin4_0 int00_2 an15 68 c7 55 - p0b j* n sot4_0 (sda4_0) tiob6_1 an16 int18_0 69 b7 56 - p0c j* n sck4_0 (scl4_0) tioa6_1 int19_0 an17 70 b6 - - p0d e l rts4_0 tioa3_2 i nt20_0 71 c6 - - p0e e l cts4_0 tiob3_2 i nt21_0 72 a6 57 42 p0f f i nmix subout_0 crout_1 rtcco_0 wkup0 an18 73 b5 - - p63 e l int03_0 74 c5 58 - p62 f m sck5_0 (scl5_0) adtg_3 an19 75 b4 59 43 p61 f m sot5_0 (sda5_0) tiob2_2 dtti0x_2 an20 d a t a s h e e t 22 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 80 bga - 96 l qfp - 64 qfn - 64 l qfp - 48 qfn - 48 76 c4 60 44 p60 j* n sin5_0 tioa2_2 int15_1 wkup3 igtrg_1 an21 77 a4 61 45 vcc - 78 a3 62 46 p80 h h int16_1 79 a2 63 47 p81 h h int17_1 80 a1 64 48 vss - - a5, a7, a11, b2, b10, c3, c9, f1, f2, f3, j3, j9, k2, k10, l6 - - vss - * : 5 v tolerant i/o d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 23 confidential ? list of functions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same f unction for the same channel. use the extended port function register (epfr) to select the pin. pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 adc adtg_0 a/d converter external trigger input pin 66 a8 - - adtg_1 7 d3 - - adtg_2 13 g3 9 5 adtg_3 74 c5 58 - adtg_6 12 g2 8 - an00 a/d converter analog input pin . anxx describes adc ch.xx . 42 j11 34 25 an01 43 j10 35 26 an02 44 j8 36 27 an04 46 h9 38 29 an05 47 g10 39 30 an06 48 g9 - - an07 49 f10 40 - an08 53 f9 44 - an09 54 e11 45 - an10 55 e10 - - an11 56 e9 - - an12 57 d10 46 34 an13 58 d9 47 35 an14 59 c11 48 36 an15 67 c8 54 - an16 68 c7 55 - an17 69 b7 56 - an18 72 a6 57 42 an19 74 c5 58 - an20 75 b4 59 43 an21 76 c4 60 44 an22 2 c1 2 2 an23 3 c2 3 3 an24 4 b3 4 4 an25 9 e2 5 - an26 10 e3 6 - d a t a s h e e t 24 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 base timer 0 tioa0_1 bas e timer ch.0 tioa pin 14 h1 10 6 tiob0_0 base timer ch.0 tiob pin 30 k6 22 18 tiob0_1 9 e2 5 - base timer 1 tioa1_1 base timer ch.1 tioa pin 15 h2 11 7 tioa1_2 5 d1 - - tiob1_0 base timer ch.1 tiob pin 31 j6 23 19 tiob1_1 10 e3 6 - tiob1_2 6 d2 - - base timer 2 tioa2_1 base timer ch.2 tioa pin 16 h3 12 8 tioa2_2 76 c4 60 44 tiob2_0 base timer ch.2 tiob pin 32 l7 24 - tiob2_1 11 g1 7 - tiob2_2 75 b4 59 43 base timer 3 tioa3_1 base timer ch.3 tioa pin 17 j1 13 9 tioa3_2 70 b6 - - tiob3_0 base timer ch.3 tiob pin 33 k7 25 - tiob3_1 12 g2 8 - tiob3_2 71 c6 - - base timer 4 tioa4_0 base timer ch.4 tioa pin 21 l5 - - tioa4_1 18 j2 14 10 tiob4_0 base timer ch.4 tiob pin 34 j7 26 - base timer 5 tioa5_0 base timer ch.5 tioa pin 22 k5 - - tioa5_1 19 j4 15 11 tiob5_0 base timer ch.5 tiob pin 35 k8 27 - base timer 6 tioa6_1 base timer ch.6 tioa pin 69 b7 56 - tiob6_1 base timer ch.6 tiob pin 68 c7 55 - base timer 7 tioa7_1 base timer ch.7 tioa pin 57 d10 46 34 ti ob7_1 base timer ch.7 tiob pin 58 d9 47 35 debugger swclk serial wire debug interface clock input pin 62 b9 50 38 swdio serial wire debug interface data input / output pin 64 a9 52 40 swo serial wire viewer output pin 65 b8 53 41 tck j - tag test cloc k input pin 62 b9 50 38 tdi j - tag test data input pin 63 b11 51 39 tdo j - tag debug data output pin 65 b8 53 41 tms j - tag test mode state input/output pin 64 a9 52 40 trstx j - tag test reset i nput pin 61 a10 49 37 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 25 confidential pin function pin name function d escription pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 external interrupt int00_0 external interrupt request 00 input pin 2 c1 2 2 int00_2 67 c8 54 - int01_0 external interrupt request 0 1 input pin 3 c2 3 3 int02_0 external interrupt re quest 0 2 input pin 4 b3 4 4 int02_1 43 j10 35 26 int03_0 external interrupt request 0 3 input pin 73 b5 - - int03_1 46 h9 38 29 int03_2 9 e2 5 - int04_0 external interrupt request 04 input pin 12 g2 8 - int04_1 49 f10 40 - int04_2 10 e3 6 - int05_0 external interrupt request 0 5 input pin 60 p20 - - int05_1 55 e10 - - int05_2 11 g1 7 - int06_ 0 external interrupt request 0 6 input pin 13 g3 9 5 int06_1 59 c11 48 36 int06_2 35 k8 27 - int07_ 0 external interrupt request 0 7 inp ut pin 14 h1 10 6 int07_2 5 d1 - - int08_2 external interrupt request 0 8 input pin 8 e1 - - int10_ 0 external interrupt request 10 input pin 21 l5 - - int11_ 0 external interrupt request 11 input pin 22 k5 - - int12_ 0 external interrupt request 12 input pin 33 k7 25 - int13_ 0 external interrupt request 13 input pin 34 j7 26 - int14_ 0 external interrupt request 14 input pin 47 g10 39 30 int14_1 29 j5 - - int15_ 0 external interrupt request 15 input pin 48 g9 - - int15_1 76 c4 60 44 int1 6_1 external interrupt request 16 input pin 78 a3 62 46 int17_1 external interrupt request 17 input pin 79 a2 63 47 int18_0 external interrupt request 18 input pin 68 c7 55 - int18_1 6 d2 - - int18_2 16 h3 12 8 int19_0 external interrupt reques t 19 input pin 59 c11 56 - int19_1 7 d3 - - int19_2 18 j2 14 10 int20_0 external interrupt request 20 input pin 70 b6 - - int20_1 30 k6 22 18 int20_2 56 e9 - - int21_0 external interrupt request 21 input pin 71 c6 - - int21_1 31 j6 23 19 int22_1 external interrupt request 22 input pin 32 l7 24 - int23_1 external interrupt request 23 input pin 66 a8 - - nmix non - maskable interrupt input pin 72 a6 57 42 d a t a s h e e t 26 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 gpio p00 general - purpose i/o port 0 61 a10 49 37 p01 62 b9 50 38 p02 63 b11 51 39 p03 64 a9 52 40 p04 65 b8 53 41 p07 66 a8 - - p0a 67 c8 54 - p0b 68 c7 55 - p0c 69 b7 56 - p0d 70 b6 - - p0e 71 c6 - - p0f 72 a6 57 42 p10 general - purpose i/o port 1 42 j11 34 25 p11 43 j10 35 26 p12 44 j8 36 27 p14 46 h9 38 29 p15 47 g10 39 30 p16 48 g9 - - p17 49 f10 40 - p18 53 f9 44 - p19 54 e11 45 - p1a 55 e10 - - p1b 56 e9 - - p20 g eneral - purpose i/o port 2 60 c10 - - p21 59 c11 48 36 p22 58 d9 47 35 p23 57 d10 46 34 p30 general - purpose i/o port 3 9 e2 5 - p31 10 e3 6 - p32 11 g1 7 - p33 12 g2 8 - p39 13 g3 9 5 p3a 14 h1 10 6 p3b 15 h2 11 7 p3c 16 h3 1 2 8 p3d 17 j1 13 9 p3e 18 j2 14 10 p3f 19 j4 15 11 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 27 confidential pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 gpio p44 general - purpose i/o port 4 21 l5 - - p45 22 k5 - - p46 26 l3 19 15 p47 27 k3 20 16 p48 29 j5 - - p49 30 k6 22 18 p4a 31 j6 23 19 p4b 32 l7 24 - p4c 33 k7 25 - p4d 34 j7 26 - p4e 35 k8 27 - p50 general - purpose i/o port 5 2 c1 2 2 p51 3 c2 3 3 p52 4 b3 4 4 p53 5 d1 - - p54 6 d2 - - p55 7 d3 - - p56 8 e1 - - p60 general - purpose i/o port 6 76 c4 60 44 p61 75 b4 59 43 p62 74 c5 58 - p63 73 b5 - - p80 general - purpose i/o port 8 78 a3 62 46 p81 79 a2 63 47 pe0 general - purpose i/o port e 36 k9 28 20 pe2 38 l9 30 22 pe3 39 l10 31 23 d a t a s h e e t 28 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 multi - function serial 0 sin0_0 multi - function serial interface ch.0 input pin 59 c11 48 36 sin0_1 46 h9 38 29 sot0_0 (sda0_0) multi - func tion serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 58 d9 47 35 sot0_1 (sda0_1) 47 g10 39 30 sck0_0 (scl0_0) multi - funct ion serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a csio (operation mode 2 ) and as scl0 when it is used in an i 2 c (operation mode 4). 57 d10 46 34 sck0_1 (scl0_1) 48 g9 - - multi - function serial 1 sin1_1 multi - funct ion serial interface ch.1 input pin 43 j10 35 26 sot1_1 (sda1_1) multi - function serial interface ch.1 output pin. this pin operates as sot 1 when it is used in a uart/ lin (operation modes 0 ,1, 3 ) . 44 j8 36 27 multi - function serial 2 sin2_ 2 multi - functio n serial interface ch.2 input pin 49 f10 40 - sot2_ 2 (sda2_ 2 ) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). 53 f9 44 - sck2_ 2 (scl2_ 2 ) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a csio (operation mode 2 ) and as scl2 when it is used in an i 2 c (operation mode 4). 54 e11 45 - multi - function serial 3 sin3_ 1 multi - function serial interface ch.3 input pin 2 c1 2 2 sin3_ 2 29 j5 - - sot3_ 1 (sda3_ 1 ) multi - function serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). 3 c2 3 3 sot3_ 2 (sda3_ 2 ) 30 k6 - - sck3_ 1 (scl3_ 1 ) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a csio (operation mode 2 ) and as scl3 when it is used in an i 2 c (operati on mode 4). 4 b3 4 4 sck3_ 2 (scl3_ 2 ) 31 j6 - - d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 29 confidential pin function pin name function description pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 multi - function serial 4 sin4_0 multi - function serial interface ch.4 input pin 67 c8 54 - sin4_1 5 5 e10 - - sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda4 when it is used in an i 2 c (operation mode 4). 68 c7 55 - sot4_1 (sda4_1) 56 e9 - - sck4_0 (scl4_0) multi - function serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a csio (operation mode 2 ) and as scl4 when it is used in an i 2 c (operation mode 4). 69 b7 56 - rts4_0 multi - function serial interface ch.4 rts output pin 70 b6 - - cts4_0 multi - function serial interface ch.4 cts input pin 71 c6 - - multi - function serial 5 sin5_0 multi - function serial interface ch.5 input pin 76 c4 60 44 sot5_0 (sda5_0) multi - function serial interface ch.5 output pi n. this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 75 b4 59 43 sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 w hen it is used in a csio (operation mode 2 ) and as scl5 when it is used in an i 2 c (operation mode 4). 74 c5 58 - multi - function serial 6 sin6_0 multi - function serial interface ch.6 input pin 5 d1 - - sin6_1 12 g2 8 - sot6_0 (sda6_0) multi - function s erial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 6 d2 - - sot6_1 (sda6_1) 11 g1 7 - sck6_0 (scl6_0) multi - function serial i nterface ch. 6 clock i/o pin. this pin operates as sck 6 when it is used in a csio (operation mode 2 ) and as scl 6 when it is used in an i 2 c (operation mode 4). 7 d3 - - sck6_1 (scl6_1) 10 e3 6 - d a t a s h e e t 30 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin function pin name function description pin no lq fp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 multi - function serial 7 sin7_ 1 multi - function serial interface ch. 7 input pin 35 k8 27 - sot7_ 1 (sda7_ 1 ) multi - function serial interface ch. 7 output pin. this pin operates as sot 7 when it is used in a uart/csi o /lin (operation modes 0 to 3 ) and as sda 7 when it is used in an i 2 c (operation mode 4). 34 j7 26 - sck7_ 1 (scl7_ 1 ) multi - function serial interface ch. 7 clock i/o pin. this pin operates as sck 7 when it is used in a csio (operation mode 2 ) and as scl 7 whe n it is used in an i 2 c (operation mode 4). 33 k7 25 - multi - function timer 0 dtti0x_0 input signal of waveform generator to control outputs rto00 to rto05 of multi - function timer 0. 13 g3 9 5 dtti0x_2 75 b4 59 43 frck0_ 2 16 - bit free - run timer ch.0 e xternal clock input pin 43 j10 35 26 ic00_1 16 - bit input capture input pin of multi - function timer 0 . icxx describes chan n el number. 55 e10 - - ic00_ 2 44 j8 36 27 ic01_1 56 e9 - - ic02_ 2 46 h9 38 29 ic03_ 2 47 g10 39 30 rto00_0 (ppg00_0) wav eform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode . 14 h1 10 6 rto01_0 (ppg00_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output mode . 15 h2 11 7 rto02_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output mode . 16 h3 12 8 rto03_0 (ppg02_0) waveform generator output pin of multi - function timer 0 . th is pin operates as ppg02 when it is used in ppg0 output mode . 17 j1 13 9 rto04_0 (ppg04_0) waveform generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode . 18 j2 14 10 rto05_0 (ppg04_0) waveform g enerator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output mode . 19 j4 15 11 igtrg_0 ppg igbt mode external trigger input pin 32 l7 24 - igtrg_1 76 c4 60 44 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 31 confidential pin function pin name function description p in no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 9 e2 5 - ain0_1 30 k6 22 - ain0_2 2 c1 2 2 bin0_0 qprc ch.0 bin input pin 10 e3 6 - bin0_1 31 j6 23 - bin0_2 3 c2 3 3 zin0_0 qprc ch.0 zin input pin 11 g1 7 - zin0_1 32 l7 24 - zin0_2 4 b3 4 4 quadrature position/ revolution counter 1 ain1_1 qprc ch.1 ain input pin 60 c10 - - ain1_2 33 k7 25 - bin1_1 qprc ch.1 bin input pin 59 c11 - - bin1_2 34 j7 26 - zin1_1 qprc ch.1 zin input pin 58 d9 - - zin1_2 35 k8 27 - real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 72 a6 57 42 rtcco_2 14 h1 10 6 subout_0 sub clock output pin 72 a6 57 42 subout_2 14 h1 10 6 low - power cons umption mode wkup0 deep standby mode return signal input pin 0 72 a6 57 42 wkup1 deep standby mode return signal input pin 1 43 j10 35 26 wkup2 deep standby mode return signal input pin 2 59 c11 48 36 wkup3 deep standby mode return signal input pin 3 76 c4 60 44 dac da0 d/a converter ch.0 analog output pin 30 k6 22 18 da1 d/a converter ch.1 analog output pin 31 j6 23 19 reset initx external reset input pin. a reset is valid when initx="l". 28 k4 21 17 d a t a s h e e t 32 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin function pin name function descriptio n pin no lqfp - 80 bga - 96 lq fp - 64 qfn - 64 lqfp - 48 qfn - 48 mode md0 mode 0 pin. during normal operation, md0="l" must be input. during serial programming to f lash memory, md0="h" must be input. 37 l8 29 21 md1 mode 1 pin. during serial programming to f la sh memory, md1="l" must be input. 36 k9 28 20 power vcc power supply pin 1 b1 1 1 vcc power supply pin 25 k1 18 14 vcc power supply pin 41 k11 33 - vcc power supply pin 77 a4 61 45 gnd vss gnd pin - f1 - - vss gnd pin - f2 - - vss gnd pin - f3 - - vss gnd pin - b2 - - vss gnd pin 20 l1 16 12 vss gnd pin - k2 - - vss gnd pin - j3 - - vss gnd pin - l6 - - vss gnd pin 24 l4 - - vss gnd pin 40 l11 32 24 vss gnd pin - k10 - - vss gnd pin - j9 - - vss gnd pin - b10 - - vss gnd pi n - c9 - - vss gnd pin - d11 - - vss gnd pin - a11 - - vss gnd pin - a7 - - vss gnd pin - c3 - - vss gnd pin - a5 - - vss gnd pin 80 a1 64 48 clock x0 main clock (oscillation) input pin 38 l9 30 22 x0a sub clock (oscillation) input pin 26 l3 19 15 x1 main clock (oscillation) i/o pin 39 l10 31 23 x1a sub clock (oscillation) i/o pin 27 k3 20 16 crout _0 built - in high - speed cr - osc clock output port 60 c10 - - crout _1 72 a6 57 42 analog power avcc a/d converter and d/a converter analog p ower supply pin 50 h11 41 31 avrh a/d converter analog reference voltage input pin 51 f11 42 32 analog gnd avss a/d converter and d/a converter gnd pin 45 h10 37 28 avrl a/d converter analog reference voltage input pin 52 g11 43 33 c pin c power supp ly stabilization capacity pin 23 l2 17 13 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 33 confidential ? i /o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma b ? cmos level hysteresis input ? pul l - up resistor : approximately 50 k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor pull - up resistor digital in put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control d a t a s h e e t 34 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? wi th pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital input digital out put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode c ontrol digital output digital output pull - up resistor control n-ch d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 35 confidential type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the di gital output p - ch transistor is always off ? +b input is available digital output digita l output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r d a t a s h e e t 36 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 18 ma , i ol = 16.5 ma digital output digital output pull - up resistor control digital input standby mode c ontrol digital out put digital output digital input standby mode c ontrol p-ch p-ch n-ch r p-ch n-ch r d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 37 confidential type circuit remarks i ? cmos level output ? cmos l evel hysteresis input ? 5 v tolerant ? with pull - up resistor control ? with standby mode control ? pul l - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transi stor is always off j ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? 5 v tolerant ? with pull - up resistor control ? with standby mode control ? pul l - up resisto r : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off k cmos level hysteresi s input digital output digital output pull - up resistor control digital input standby mode c ontrol digital out put digital output pull - up resistor control digital input standby mode c ontrol analog input input control mode input p-ch p-ch n-ch r p-ch p-ch n-ch r d a t a s h e e t 38 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential type circuit remarks l ? cmos level output ? cmos level hysteresis input ? with input control ? analog output ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - c h p - c h n - c h a n a l o g o u t p u t r d i g i t a l o u t p u t d i g i t a l o u t p u t d i g i t a l i n p u t s t a n d b y m o d e c o n t r o l p u l l - u p r e s i s t o r c o n t r o l d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 39 confidential ? handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product design this section describes precautions when designing electronic equip ment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exce ed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconduc tor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconducto r devices to power supply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance ca n cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely af fect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to a bnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: t he occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not ex ceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 3 e d a t a s h e e t 40 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? observance of safety regulations and standards m ost countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design a ny semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevent ion of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, c ommunications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or p roperty damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales repr esentatives before such use. the company will not be responsible for damages arising from such use without prior approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circui t boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) met hod of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditio ns. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch resu lts in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with spansion ranking of recommended conditions. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 41 confidential ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the appli cation of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense i nside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that rec ommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storag e. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c /24 h ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparat us for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through h igh resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hi ghly static - prone materials for storage of completed board assemblies. d a t a s h e e t 42 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following : (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exis t close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to c hemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments invo lving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn , there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. ht tp://www.spansion.com/fjdocuments/fj/datasheet/e - ds/ds00 - 00004.pdf d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 43 confidential ? handling devices ? power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to preven t malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the gro und level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be conne cted as a bypass capacitor between each power supply pin and gnd pin , between avcc pin and avss pin, between avrh pin and avrl pin near this device. ? stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly e ven though the fluctuation is within the recommended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple ( peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. ? crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circui t board so that x0 / x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrou nded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. ? sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ? surface mount type size : more than 3.2 mm 1.5 mm load capacitance : approximately 6 pf to 7 pf ? lead type load capacitanc e : approximately 6 pf to 7 pf d a t a s h e e t 44 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? using an external clock when using an external cloc k as an input of the main clock , set x0 / x1 to the external clock input, and input the clock to x0 . x1 (pe3) can be used as a general - purpose i/o port. similarly, w hen using a n external cloc k as an input of the sub clock , set x0 a/ x1 a to the external clock input, and input the clock to x0 a. x1 a (p47) can be used as a general - purpose i/o port. ? handling when using multi - function serial pin as i 2 c pi n if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disable d . however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. ? c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. h owever, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. ? mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between th e mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously s witching to test mode due to noise. ? example of using an external clock device x0 ( x0a ) x1 (pe3), x1a (p47) can be used as general - purpose i/o ports. device c vss c s gnd set as external clock input d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 45 confidential ? notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter and d/a converter , connect avcc = vcc and avss = vss. turning on : vcc ? serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. ? differences in features among the products with different memory sizes and between flash memory products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash memory products and mask pro ducts are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. ? pull - up function of 5 v tolerant i / o please do not i nput the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i / o. d a t a s h e e t 46 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? block diagram ? memory size see " ? memory size " in " ? product lineup " to confirm the memory size. m b 9 b f 1 2 1 k / l / m , f 1 2 2 k / l / m , f 1 2 4 k / l / m c o r t e x - m 3 f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . w a t c h c o u n t e r c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i p o w e r - o n r e s e t s r a m 0 8 / 1 6 k b y t e s s r a m 1 8 / 1 6 k b y t e s i d s y s n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r t r s t x , t c k , t d i , t m s a v c c , a v s s , a v r h , a v r l a n x x t i o a x t i o b x c t d o s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , ? ? ? p f x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r c r c a c c e l e r a t o r a d t g x r t s 4 c t s 4 o n - c h i p f l a s h 6 4 + 3 2 k b y t e s / 1 2 8 + 3 2 k b y t e s / 2 5 6 + 3 2 k b y t e s m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 0 / 1 / 3 / 4 ) h w f l o w c o n t r o l ( c h . 4 ) g p i o p i n - f u n c t i o n - c t r l l v d r o m t a b l e s w j - d p l v d c t r l b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . r e a l - t i m e c o l c k r t c c o _ x , s u b o u t _ x d e e p s t a n d b y c t r l w k u p x u n i t 0 u n i t 1 1 0 - b i t d / a c o n v e r t e r 2 u n i t s d a x q p r c 2 c h . a i n x b i n x z i n x m u l t i - f u n c t i o n t i m e r 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 2 c h . 1 6 - b i t p p g 3 c h . i c 0 x d t t i 0 x r t o 0 x f r c k x i g t r g _ x a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) a h b - a h b b r i d g e m u l t i - l a y e r a h b ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z ) x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z x 1 a d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 47 confidential ? memory map ? memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0xe000_0000 0x4006_1000 0x4006_0000 dmac 0x4003_c000 0x4003_b000 rtc 0x7000_0000 0x4003_a000 watch counter 0x4003_9000 crc 0x6000_0000 0x4003_8000 mfs 0x4003_6000 0x4400_0000 0x4003_5000 lvd/ds mode 0x4003_4000 reserved 0x4200_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4000_0000 0x4003_1000 int-req.read 0x4003_0000 exti 0x2400_0000 0x4002_f000 reserved 0x4002_e000 cr trim 0x2200_0000 0x4002_9000 reserved 0x4002_8000 d/ac 0x2008_0000 0x4002_7000 a/dc 0x2000_0000 sram1 0x4002_6000 qprc 0x1ff8_0000 sram0 0x4002_5000 base timer 0x4002_4000 ppg 0x0020_8000 0x0020_0000 flash(work area) 0x0010_4000 reserved 0x4002_1000 0x0010_0000 security/cr trim 0x4002_0000 mft unit0 0x4001_6000 0x4001_5000 dual timer 0x4001_3000 0x0000_0000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f see " ? memory map (2)" for the memory size details. 32mbytes bit band alias reserved reserved reserved reserved cortex-m3 private peripherals 32mbytes bit band alias reserved reserved reserved reserved peripherals reserved reserved reserved reserved reserved external device area flash(main area) d a t a s h e e t 48 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? memory map (2) r efer to the programming manual for the detail of fla sh main area. ? mb9ab40n/a40n/340n/140n/150r,mb9b520m/320m/120m series flash programming manual mb9bf124k/l/m MB9BF122K/l/m mb9bf121k/l/m 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_e000 0x1fff_e000 0x1fff_c000 0x0020_8000 0x0020_8000 0x0020_8000 sa7(8kb) sa7(8kb) sa7(8kb) sa6(8kb) sa6(8kb) sa6(8kb) sa5(8kb) sa5(8kb) sa5(8kb) 0x0020_0000 sa4(8kb) 0x0020_0000 sa4(8kb) 0x0020_0000 sa4(8kb) 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x0004_0000 0x0002_0000 0x0001_0000 sa3(8kb) sa3(8kb) sa3(8kb) 0x0000_0000 sa2(8kb) 0x0000_0000 sa2(8kb) 0x0000_0000 sa2(8kb) flash(main area) 64kbytes sa8(48kb) sa8(48kb) sa8(48kb) reserved reserved sa11(64kb) flash(main area) 256kbytes sa10(64kb) sa9(64kb) sa9(64kb) flash(main area) 128kbytes flash(work area) 32kbytes reserved reserved reserved reserved sram1 8kbytes sram1 8kbytes sram0 8kbytes sram0 8kbytes reserved reserved flash(work area) 32kbytes sram0 16kbytes sram1 16kbytes reserved reserved reserved flash(work area) 32kbytes reserved d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 49 confidential ? peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0 x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_ 3 fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter (qprc) 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_8 fff d /a converter 0x4002_ 9 000 0x4002_dfff reserved 0x4002_e000 0x4002_efff built - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt 0x4003_1000 0x4003_1fff interrupt source check register 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5 7 ff low - voltage detector 0x4003_ 58 00 0x4003_5 f ff deep standby mode controller 0x4003_ 6 000 0x4003_7fff reser ved 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_ f fff reserved 0x4004_0000 0x400 5 _ffff ahb reserved 0x4006_ 0000 0x4006_0fff dmac register 0x4006_ 1 000 0x41ff_ffff reserved d a t a s h e e t 50 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the " l " level. ? initx=1 this is the period when the initx pin is the " h " level. ? spl=0 this i s the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 0 " . ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 1 " . ? inpu t enabled indicates that the input function can be used. ? internal input fixed at " 0 " this is the status that the input function cannot be used. internal input is fixed at " l " . ? hi - z indicates that the pin drive transistor is disabled and the pin is put in t he hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral f unction. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. ? gpio selected in deep standby mode, pins switch to the g eneral - purpose i/o port. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 51 confidential ? list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external main clock input se lected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state main crystal oscillator output pin hi - z / internal input fixed at "0"/ or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation st op s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stop s * 1 , hi - z / internal input fixed at "0" c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous st ate hi - z / input enabled gpio selected hi - z / input enabled gpio selected d a t a s h e e t 52 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fi xed at "0" hi - z / internal input fixed at "0" gpio selected sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled g gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external su b clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state sub crystal os cillator output pin hi - z / internal input fixed at " 0 " / or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state maintain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" main tain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" ma intain previous state /when oscillation stop s * 2 , hi - z / internal input fixed at "0" h external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selec ted internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 53 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - i analog input selected hi - z hi - z / internal input fixed at "0" / analo g input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / i nternal inpu t fixed at "0" / analog input dis abled hi - z / internal inpu t fixed at "0" / analog input dis abled hi - z / internal input fixed at "0" / analog input dis abled nmix selected setting disabled setting disabled setting disabled maintain previous s tate maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected maintain previous state j jtag selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state gpio selecte d setting disabled setting disabled setting disabled hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected k resource selected hi - z hi - z / input enabled hi - z / input enabled maint ain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected l analog output selected setting disabled setting disabled se tting disabled maintain previous state *3 *4 gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external interrupt enabled selected maintain previous state maintain previous state resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected d a t a s h e e t 54 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - m analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog i nput enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / inte rnal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / interna l input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected n analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabl ed hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z / internal input fixed at "0" gpio selected *1 : oscillation is stopped at s ub t imer mode , low - speed cr t imer mode, rtc mode, s top mode , deep s tandby rtc mode , and deep s tandby s top mode. *2 : oscillation is stopped at s top mode and deep s tandby s top mode . * 3 : maintain previous state at t imer mode . gpio selected i nternal input fixed at "0" at rtc mode , s top mode. * 4 : maintain previous state at t imer mode. hi - z/internal input fixed at "0" at rtc mode, s top mode. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 55 confidential ? electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1 , * 2 v cc vss - 0.5 v ss + 6.5 v analog power supply voltage * 1 , * 3 av cc v ss - 0.5 v ss + 6.5 v analog reference voltage * 1 , * 3 avrh v ss - 0.5 v ss + 6.5 v input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( ss - 0.5 v ss + 6.5 v 5 v tolerant analog pin input voltage* 1 v ia v ss - 0.5 av cc + 0.5 ( 1 v o v ss - 0.5 v cc + 0.5 ( clamp - 2 +2 ma * 7 clamp total maximum current clamp ] +20 ma * 7 l level maximum output current* 4 i ol - 10 ma 4 ma type 20 ma 12 ma type 39 ma p80/p81 pin l level average output current* 5 i olav - 4 ma 4 ma type 12 ma 12 ma type 16.5 ma p80/p81 pin l level total maximum output current ol - 100 ma l level total average output current* 6 olav - 50 ma h level maximum output current* 4 i oh - - 10 ma 4 ma type - 20 ma 12 ma type - 39 ma p80/p81 pin h level average output current* 5 i ohav - - 4 ma 4 ma type - 12 ma 12 ma ty pe - 18 ma p80/p81 pin h level total maximum output current oh - - 100 ma h level total average output current* 6 ohav - - 50 ma power consumption p d - 300 mw storage temperature t stg - 55 + 150 c * 1 : the se parameters are based on the condition that v ss = a v ss = 0 v. * 2 : v cc must not drop below v ss - 0.5 v. * 3 : ensure that the voltage does not exceed v cc + 0. 5 v , for example , when the power is turned on. * 4 : the maximum output current is defined as the value of the peak current flow ing through any one of the corresponding pins . * 5 : the average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. * 6 : the total average output current is defined as the average cu rrent value flowing through all of corresponding pins for a 100 ms period. d a t a s h e e t 56 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential * 7 : ? see " ? list of pin functions " and " ? i/o circuit type " about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the + b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consumpsion modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, an d this may affect other devices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example (i/o equivalent circuit ) . < warning > semiconductor devices can be permanently damaged by application of stress (voltage , current , temperature , etc.) in excess of absolute maximum ratings. do not exc eed these ratings. r +b input (0v to 16v) protection diode p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 57 confidential 2. recommended operating conditions (v ss = av ss = avrl = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc - 2.7 * 2 5.5 v analog power supply voltage av cc - 2.7 5.5 v av cc = v cc analog referenc e voltage avrh - 2.7 av cc v avrl - av ss av ss v smoothing capacitor c s - 1 10 f 1 operating t emperature t a - - 40 + 10 5 c * 1 : see " ? c pin" in " ? handling devices " for the connection of the smoothing capacitor. *2 : in between less than the minimum power supply voltage and low voltage reset/inte rrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or bulit - in low - speed cr is possible to operate only . < warning > the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condit ion ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses , operating conditions , or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. d a t a s h e e t 58 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential 3. dc characteristics ( 1 ) current rating (v cc = av cc = 2.7v to 5.5v , v ss = av ss = avrl = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit r emarks typ max r un mode current i cc v cc pll r un mode cpu : 72 mhz , peripheral : 36 mhz 32.5 41 ma *1 , *5 cpu:72mhz, peripheral clock stops nop operation 18 23 ma *1 , *5 high - speed cr r un mode cpu/ peripheral : 4mhz* 2 2.5 3.4 ma *1 sub r un mode cpu/ peripheral : 32khz 110 980 a *1 , * 6 low - speed cr r un mode cpu/ peripheral : 100khz 130 1030 a *1 s leep mode current i ccs pll s leep mode peripheral : 36 mhz 22 28 ma *1 , *5 high - speed cr s leep mode peripheral : 4mhz* 2 1.6 2.6 ma *1 sub s leep mode peripheral : 32khz 96 955 a *1 , * 6 low - speed cr s leep mode peripheral : 100 khz 115 975 a *1 *1 : when a l l ports are fixed. *2 : when setting it to 4 mhz by trimming. * 3 : t a =+25c, v cc = 5.5 v * 4 : t a =+ 105 c, v cc =5.5 v *5 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 59 confidential ( v cc = av cc = 2.7v to 5.5v, v ss = av ss = avr l = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks typ * 2 max * 2 timer mode current i cc t vcc main timer mode t a = + 25 c , when lvd is off 4.1 4.8 m a *1 , * 4 t a = + 105 c , when lvd is off - 5.4 m a *1 , * 4 i cc t sub timer mode t a = + 25 c , when lvd is off 17 66 a = + 105 c , when lvd is off - 835 cc r rtc mode t a = + 25 c , when lvd is off 15 61 a = + 105 c , when lvd is off - 680 cc h stop mode t a = + 25 c , when lvd is of f 14 53 a = + 105 c , when lvd is off - 600 cc rd deep standby rtc mode t a = + 25 c , when lvd is off , when ram is off 2.2 11 a = + 25 c , when lvd is off , when ram is on 6.2 23 a = + 105 c , when lvd is off , when ram is off - 155 a = + 105 c , when lvd is off , when ram is on 215 cc h d deep standby stop mode t a = + 25 c , when lvd is off , when ram is off 1.6 9.6 a = + 2 5 c , when lvd is off , when ram is on 5.6 22 a = + 105 c , when lvd is off , when ram is off - 150 a = + 105 c , when lvd is off , when ram is on 210 cc =5.5 v *3: ram on/off sett ing is on - chip sram only. * 4 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 5 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) d a t a s h e e t 60 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential low - v oltage d etection current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cc lvd vcc at operation for reset vcc = 5.5 v 0.13 0.3 flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rit e/ e rase current i ccflash vcc at write/erase 9.5 11.2 ma * *: the current at which to write or erase flash memory, " i ccflash " is added to " i cc " . a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.69 0.90 ma at stop 0.25 25.84 ccavrh avrh at 1unit operation avrh=5.5 v 1.1 1.97 ma at stop 0.2 3.4 d/a converter current ( v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value u nit remarks min typ max power supply current * 1 idda * 2 avcc at 1unit operation av cc =3.3 v 250 315 380 cc =5.0 v 380 475 580 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 61 confidential ( 2 ) pin characteristics (v cc = av cc = 2.7v to 5.5v , v ss = av ss = avrl = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin , md0 , md1 - v cc 0.8 - v cc + 0.3 v 5v tolerant input pin - v cc 0.8 - v ss + 5.5 v l level input voltage (hysteresis input) v ils cmos hysteresis input pin , md0 , md1 - v ss - 0.3 - v cc 0.2 v 5 v tolerant input pin - v ss - 0.3 - v cc 0.2 v h level output voltage v oh 4 ma type v cc oh = - 4 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 2 ma 12 ma type v cc oh = - 12 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 8 ma p80, p81 v cc oh = - 18.0 m a v cc - 0.4 - v cc v v cc < 4.5 v , i oh = - 12.0 ma l level output voltage v ol 4 ma type v cc ol = 4 ma v ss - 0.4 v v cc < 4.5 v , i ol = 2 ma 12 ma type v cc ol = 12 ma v ss - 0.4 v v cc < 4.5 v , i ol = 8 ma p80, p81 v cc ol = 16.5 ma v ss - 0.4 v v cc < 4.5 v , i ol = 10.5 ma input leak current i il - - - 5 - + 5 pu pull - up pin v cc cc < 4.5 v - - 180 input capacitance c in other than v cc, vss, avcc, avss, avrh , avrl - - 5 15 pf d a t a s h e e t 62 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential 4. ac characteristics (1) main clock input characteristics (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max input frequency f c h x0 , x1 v cc cc < 4.5 v 4 20 v cc cc < 4.5 v 4 20 input clock cycle t cylh v cc cc < 4.5 v 50 250 in put clock pulse width - p wh /t cylh , p wl /t cylh 45 55 % when using external c lock input clock rising time and falling time t cf , t cr - - 5 ns when using external c lock internal operating c lock frequency * 1 f cm - - - 72 mhz master clock f cc - - - 72 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock * 2 f cp1 - - - 40 mhz apb1 bus clock * 2 f cp 2 - - - 40 mhz apb2 bus clock * 2 internal operating clock cycle time * 1 t cy cc - - 13.8 - ns base clock (hclk/fclk) t cycp 0 - - 25 - ns apb0 bus clock * 2 t cycp 1 - - 25 - ns apb1 bus clock * 2 t cycp 2 - - 25 - ns apb2 bus clock * 2 * 1 : for more information about each internal operating clock , see " chapter 2 - 1 :clock " in " fm3 family peripheral manual ". * 2 : for about each apb bus which each peripheral is conn ected to , see " ? block diagram " in this data sheet. x0 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 63 confidential (2) sub clock input characteristics (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/ t cyll x0a , x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 wh /t cyll , p wl /t cyll 45 - 55 % when using external clock * : see " ? s ub crystal oscillator " in " ? handling devices " for the crystal oscillator used . x0 a d a t a s h e e t 64 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential (3) built - in cr oscillation characteristics ? built - in high - speed cr (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c 3.9 2 4 4.0 8 mhz when trimming * 1 t a = 0 c to + 8 5 c 3.9 4 4.1 t a = - 4 0 c to + 10 5 c 3.88 4 4.12 t a = + 25 c v cc a = - 2 0 c to + 8 5 c v cc a = - 2 0 c to + 10 5 c v cc a = - 40 c to + 10 5 c 2.8 4 5.2 when not trimming frequency stabilization time t crwt - - - 30 2 * 1 : in the case of u sing the values in cr trimming area of f lash memory at shipment for frequency /t emperature trimming. *2: this is the time to stabilize the frequency of high - speed cr clock after setting trimming value. this period is able to use high - speed cr clock as sour ce clock. ? built - in low - speed cr (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 65 confidential (4 - 1 ) operating conditions of main pll (in the case of using main clock for input of pll) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 4 - 16 mh z pll multiplication rate - 5 - 37 multiplier pll macro oscillation clock frequency f pllo 75 - 150 mh z main pll clock frequency* 2 f clkpll - - 72 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for mo re information about main pll clock (clkpll), see "chapter: clock" in "fm3 family peripheral manual". (4 - 2) operating conditions of main pll (in the case of using built - in high - speed cr for input clock of m ain pll ) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 3.8 4 4.2 mh z pll multiplication rate - 19 - 35 multiplier pll macro oscillation clock frequency f pllo 72 - 150 mh z main pll clock frequency* 2 f clkpll - - 72 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see "chapter 2 - 1 : clock " in "fm3 family peripheral manual". note: make sure to input to the m ain pll source clock, the high - speed cr clock (clkhc) that the frequency /temperature has been trimmed. when setting pll multiple rate, please take the accuracy of the built - in high - spee d cr clock into account and prevent the master clock from exceeding the maximum frequency. k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection d a t a s h e e t 66 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential (5) reset input characteristics (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max r eset input time t initx initx - 500 - ns (6) power - on reset timing (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name value unit remarks min max power supply rising time t vccr v cc 0 - ms power supply shut down t ime t off 1 - ms time until releasing power - on reset t prt 1.34 18.6 ms glossary ? vcc_minimum : minimum v cc of recommended operating conditions ? vd h _minimum : minimum detection voltage (w hen svhr=0 0 000) of low - v oltage detection reset see " 7 . low - v oltage detection characteristics " 0 . 2 v v d h _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r e s e t v c c c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e t v c c r 0 . 2 v 0 . 2 v t o f f d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 67 confidential ( 7 ) base timer input timing ? timer input timing (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit rem arks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck , t in) - 2 t cycp - ns ? trigger input timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note: t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is connected to , see " ? block diagram " in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l d a t a s h e e t 68 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ( 8 ) csio /uart timing ? csio (spi = 0 , scinv = 0) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sck x master mode 4t cycp - 4t cycp - ns sck slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin ivshi sckx , sinx 50 - 30 - ns sck shixi sckx , sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck slove sckx , sotx - 50 - 30 ns sin ivshe sckx , sinx 10 - 10 - ns sck shixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle ti me. about the apb bus number which multi - function serial is connected t o , see " ? ? these characteristics only guarantee the same relocate port number. for example , the combination of sc kx_0 and sotx_1 is no t guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 69 confidential master mode slave mode t slsh t shs l v ih t f t r v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi sck sot sin d a t a s h e e t 70 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? csio (spi = 0 , scinv = 1 ) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin ivsli sckx , sinx 50 - 30 - ns sck slixi sckx , sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck shove sckx , sotx - 50 - 30 ns sin ivsle sckx , sinx 10 - 10 - ns sck slixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is co nnected to , see " ? ? these characteristics only guarantee the same relocate port number. for example , the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 71 confidential master mode slave mode t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin d a t a s h e e t 72 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? csio (spi = 1 , scinv = 0 ) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin ivsli sckx , sinx 50 - 30 - ns sck slixi sckx , sinx 0 - 0 - ns sot sovli sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck shove sckx , s ot x - 50 - 30 ns sin ivsle sckx , sinx 10 - 10 - ns sck slixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - funct ion serial is connected to , see " ? ? these characteristics only guarantee the same relocate port number. for example , the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 73 confidential master mode slave mode *: changes when writing to tdr register t f t r t slsh t shsl t shove v i l v i l v ih v ih v ih v oh * v o l v oh v o l v ih v i l v ih v i l t ivsle t slixe sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivsli t slixi sck sot sin d a t a s h e e t 74 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? csio (spi = 1 , scinv = 1 ) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parame ter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin ivshi sckx , sinx 50 - 30 - ns sck shixi sckx , sinx 0 - 0 - ns sot sovhi sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck slove sckx , s ot x - 50 - 30 ns sin ivshe sckx , sinx 10 - 10 - ns sck shixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function ser ial is connected to , see " ? ? these characteristics only guarantee the same relocate port number. for example , the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 75 confidential master mode slave mode ? uart e xternal clock input (ext = 1 ) (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol conditions min max unit remarks serial clock l pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock h pulse width t shsl t cycp + 10 - ns sck falling time t f - 5 ns sck rising time t r - 5 ns t shsl v i l v i l v i l v ih v ih t r t f t slsh s ck t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin d a t a s h e e t 76 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ( 9 ) external i nput t iming (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl adtg - 2 t cycp * 1 - n s a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * 1 - ns waveform generator int xx , nmix *2 2 t cycp + 1 00 * 1 - ns external interrupt nmi *3 500 - ns wkupx *4 500 - ns deep standby wake up *1 : t cycp indicates the apb bus clock cycle time . about the apb bus number which the a/d converter , multi - function timer , external interrupt are connected t o , see " ? block diagram " in this data sheet. *2: when in r un mode, in s leep mode. * 3 : when in s top mode, in rtl mode, in t imer mode. * 4 : when in deep s tandby rtc mode, in deep s tandby s top mode. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 77 confidential (1 0 ) quadrature position/revolution counter timing (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol conditions value unit min max ain pin h width t ahl - 2 t cycp * - ns ain pin l width t all - bin pin h width t bhl - bin pin l width t bll - bin rising time from ain pin h level t aubu pc_mode2 or pc _ m ode3 ain falling time from bin pin h level t buad pc_mode2 or pc_mode3 bin falling time from ain pin l level t adbd pc_mode2 or pc_mode3 ain rising time from bin pin l level t bdau pc_mode2 or pc_mode3 ain rising time from bin pin h level t buau pc_mode2 or pc_mode3 bin falling time from ain pin h level t aubd pc_mode2 or pc_mode3 ain falling time from bin pin l level t bdad pc_mode2 or pc_mode3 bin rising time from ain pin l level t adbu pc_mode2 or pc_mode3 zin pin h width t zhl qcr:cgsc= 0 zin pin l width t zll qcr:cgsc= 0 ain/bin rise and falling time from determined zin level t zabe qcr:cgsc= 1 determined zin level from ain/bin rise and falling time t abez qcr:cgsc= 1 *: t cycp indicate s the apb bus clock cycle time . about the apb bus number which the quadrature position/revolution counter is connected t o , see " ? block diagram " in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll d a t a s h e e t 78 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 79 confidential (1 1 ) i 2 c t iming (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf , r = (v p /i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda hdsta 4.0 - 0.6 - low 4.7 - 1.3 - high 4.0 - 0.6 - susta 4.7 - 0.6 - hddat 0 3.45* 2 0 0.9* 3 sudat 250 - 100 - ns stop condition setup time scl susto 4.0 - 0.6 - buf 4.7 - 1.3 - sp - 2 t cycp * 4 - 2 t cycp * 4 - ns *1 :r and c l represent the pull - up resistor and load capacitance of the scl and sda lines, respectively. v p indicates the power supply voltage of the pull - up resistor and i ol indicates v ol guaranteed current. *2 :the maximum t hddat must satisfy that it does not extend at least l period (t low ) of device's scl signal. *3 : a fast - speed mode i 2 c bus device can be used on a s tandard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4 :t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is connected to, see " ? block diagram " in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more to use fast - mode , set the apb bu s clock at 8 mhz or more. sda s cl d a t a s h e e t 80 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential (1 2 ) jtag t iming (v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 10 5 c ) parameter symbol pin name co nditions value unit remarks min max tms , tdi setup time t jtags tck , tms , tdi v cc cc < 4.5 v tms , tdi hold time t jtagh tck , tms , tdi v cc cc < 4.5 v tdo delay time t jtagd tck , tdo v cc cc < 4.5 v - 45 note: when the external load capacitance c l = 30 pf . tck tms/ tdi tdo d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 81 confidential 5. 12 - bit a/d converter ? electrical c haracteristics for the a/d c onverter (v cc = av cc = 2.7v to 5.5v , v ss = av ss = avrl = 0v , t a = - 4 0 c to + 10 5 c ) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 1.5 4.5 lsb avrh = 2.7 v to 5.5 v differential non linearity - - - 1.7 2.5 lsb zero transition v oltage v z t an xx - 10 15 mv full - scale transition voltage v fst an xx - avrh 5 avrh 15 mv conversion time - - 0.8 * 1 - - cc 1 - - av cc < 4.5 v sampling time* 2 t s - 0.24 - 10 cc cc < 4.5 v compare clock cycle* 3 t cck - 40 - 1000 ns av cc cc < 4.5 v state transition time to operation permission t stt - - - 1.0 ain - - - 9.7 pf analog input resistor r ain - - - 1.7 k cc cc < 4.5 v interchannel disparity - - - - 4 lsb analog port input current - a n xx - - 5 cc v - avrl av ss - av ss v *1: the conversion time is the value of sampling time ( t s ) + compare time ( t c ). the condition of the minimum conversion time is the following. av cc 4.5 v , hclk= 5 0 mhz sampling time: 240 ns , compare time: 560 n s . av cc < 4.5 v, hclk= 40 mhz sampling time: 3 00 ns, compare time: 700 ns ensure that it satisfies the value of the sampling time ( t s ) and compare clock cycle ( t cck ). for setting of the sampling time and compare clock cycle , see " chapter 1 - 1 : a/d converter " in " fm3 family peripheral manual analog macro part " . the register setting s of the a / d c onverter are reflected in the operation according to the apb bus clock timi ng. for the number of the apb bus to which the a/d converter is connected, see " ? block diagram ". the base clock (hclk) is used to generate the sampling time and the compare clock cycle. *2: a necessary sampling time changes by external impedan ce. ensure that it set s the sampling time to satisfy ( equation 1 ) . *3: the compare time ( t c ) is the value of ( equation 2) . d a t a s h e e t 82 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential (equation 1) t s ( r ain + r ext ) c ain 9 t s : sampling time r ain : input re sistor of a/d = 1.5 k at 4.5 v < av cc < 5.5 v ch . 0 to ch . 7 input resistor of a/d = 1.6 k at 4.5 v < av cc < 5.5 v ch . 8 to ch . 15 input resistor of a/d = 1.7 k at 4.5 v < av cc < 5.5 v ch . 16 to ch . 26 input resistor of a/d = 2.2 k at 2.7 v < av cc < 4 . 5 v ch . 0 to ch . 7 input resistor of a/d = 2.3 k at 2.7 v < av cc < 4 .5 v ch . 8 to ch . 15 input resistor of a/d = 2.4 k at 2.7 v < av cc < 4 .5 v ch . 16 to ch . 26 c ain : input capacity of a/d = 9.7 pf at 2.7 v < av cc < 5.5 v r ext : output impedance of e xternal circuit (equation 2 ) t c = t cck 14 t c : compare time t cck : compare clock cycle r ext r ain c ain analog s ignal source an xx analog input pin c omparator d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 83 confidential ? definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion ch aracteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to ch ange the output code by 1 lsb. integral nonl inearity of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential non linearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v zt 4094 n : a/d converter digital output value. v zt : voltage at whi ch the digital output ch anges from 0x000 to 0x001. v fst : voltage at whi ch the digital output ch anges from 0xffe to 0xfff. v nt : voltage at whi ch th e digital output ch anges from 0x(n ? 1) to 0xn. integral non l inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actua l conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f f d 0x f fe 0x f ff avrl avrh avrl avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t d a t a s h e e t 84 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential 6. 10 - bit d /a converter ? electrical ch aracteristics for the d /a converter ( v cc = av cc = 2.7 v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 10 5 c ) parameter symbol pin name value unit remarks min t yp max resolution - dax - - 10 bit conversion time t c20 0. 4 7 0.5 8 0.69 c100 2.37 2. 90 3.4 3 1 inl - 4.0 - + 4.0 lsb differential non linearity * 1, * 2 dnl - 0.9 - + 0.9 lsb output vol tage offset v off - - 10.0 mv code is 0x000 - 20 .0 - + 5. 4 mv code is 0x3ff analog output impedance r o 3.10 3. 8 0 4.5 0 k r - - 70 ns *1: no - load *2: generates the max current by the code about 0x200 d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 85 confidential 7. low - v oltage d etection ch aracteristics (1) l ow - v oltage d etection r eset ( t a = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr * 1 = 0 0000 2.25 2.45 2.65 v when voltage drops released voltage vdh 2.30 2.50 2.70 v when voltage rises detected voltage vdl svhr * 1 = 0 0001 2.39 2.60 2.81 v when voltage drops released voltage vdh 2.48 2.70 2.92 v when voltage rises detected voltage vdl svhr * 1 = 0 0010 2.48 2.70 2.92 v when voltage drops released voltage vdh 2.58 2.80 3.02 v when voltage rises detected voltage vdl svhr * 1 = 0 0011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhr * 1 = 0 0100 2.76 3.0 0 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhr * 1 = 0 0101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhr * 1 = 0 0110 3.31 3.60 3.89 v when voltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhr * 1 = 0 0111 3.40 3.70 4.00 v when voltage drops released voltage vdh 3.50 3.80 4.10 v when voltage rises detected voltage vdl svhr * 1 = 0 1000 3.68 4.00 4.32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhr * 1 = 0 1001 3.77 4.10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises de tected voltage vdl svhr * 1 = 0 1010 3.86 4.20 4.54 v when voltage drops released voltage vdh 3.96 4.30 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 8160 t cycp * 2 lvddl - - - 200 cycp indicates the apb2 bus clock cycle time. d a t a s h e e t 86 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ( 2 ) interrupt of l ow - v oltage d etection ( t a = - 40 c to + 10 5 c ) parameter symbo l conditions value unit remarks min typ max detected voltage vdl svhi = 0 0011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 0 0100 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 0 0101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhi = 0 0110 3.31 3.60 3.89 v when v oltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhi = 0 0111 3.40 3 . 70 4.00 v when voltage drops released voltage vdh 3.50 3 . 8 0 4.10 v when voltage rises detected voltage vdl svhi = 0 1000 3.68 4 . 00 4. 32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhi = 0 1001 3.77 4 . 10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises detected voltage vdl svhi = 0 1010 3 .86 4 . 20 4.54 v when voltage drops released voltage vdh 3.96 4. 3 0 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 8160 t cycp * lvddl - - - 200 cycp indicates the apb2 bus clock cycle time. d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 87 confidential 8. flash memory write/erase ch aracteristics (1) write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 10 5 c ) parameter value unit remarks typ max sector erase time large sector 1.1 2.7 s includ es write time prior to internal erase small se ctor 0.3 0.9 half word (16 - bit) write time 16 310 (2) write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1 , 000 20* 10 , 000 10* * : at average + 85 ? c d a t a s h e e t 88 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential 9. return time from low - power consumption mode (1 ) return f actor: interrupt/wkup the return time from low - power consumption mode is indicated as follo ws. it is from receiving the return factor to starting the program operation. ? return c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* s leep mode t icnt t cycc 40 80 340 680 680 860 268 503 308 583 268 503 ? operation example of return from l ow - p ower consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 89 confidential ? operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "chapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "c hapter 6 : low power consumption mode" in "fm3 family peripheral manual". i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t 90 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential (2) return f actor: reset the return time from low - power cons umption mode is indicated as follows. it is from releasing reset to starting the program operation. ? return c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* s leep mode t rcnt 14 8 26 3 ? operation example of return from l ow - p ower consumption mode (by initx) i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 91 confidential ? operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "chapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "c hapter 6 : low power consumption mode" in "fm3 family p eripheral manual". ? the time during the power - on reset/low - voltage detection reset is excluded. see " (6) power - on reset timing in 4. ac characteristics in ? ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the m ain pll clock st abilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e d a t a s h e e t 92 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? ordering information part number on - chip flash memory on - chip sram package packing mb9bf 1 2 1 kqn - g - ave2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? qf n (0.5 mm pitch ), 48 - pin ( lcc - 48p - m73 ) tray mb9bf 1 2 2 kqn - g - ave2 main: 128 kbyte work : 32 kbyte 16 kbyte mb9bf 1 2 4 kqn - g - ave2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 1 2 1 k pmc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp (0.5 mm pitch ), 48 - pin ( fpt - 48p - m49 ) mb9bf 1 2 2 k pmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 2 4 k pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 1 21 l qn - g - ave2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? qfn (0. 5 mm pitch ), 64 - pin ( lcc - 64p - m24 ) mb9bf 1 22lqn - g - ave2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 24lqn - g - ave2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 1 2 1 l pmc 1 - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp (0.5 mm pitch ), 64 - pin ( fpt - 64p - m38 ) mb9bf 1 2 2 l pmc 1 - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 24l pmc 1 - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 1 2 1 lpmc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? l qfp (0.65 mm pitch ), 64 - pin (fpt - 64p - m39 ) mb9bf 1 2 2 lpmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 2 4 lpmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 1 2 1 m pmc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp (0.5 mm pitch ), 80 - pin ( fpt - 80p - m37 ) mb9bf 1 2 2 m pmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 24m pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 1 2 1 mp mc1 - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? l qfp (0.65 mm pitch ), 80 - pin ( fpt - 80p - m40 ) mb9bf 1 2 2 mpmc1 - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 2 4 mpmc1 - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3v0 - e 93 confidential part number on - chip flash memory on - chip sram package packing mb9bf 1 21m bgl - ge1 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? pfbga (0. 5 mm pitch ), 96 - pin ( bga - 96p - m07 ) tray mb9bf 1 22m bgl - ge1 main: 128 kbyte work: 32 kbyte 16 kbyte mb9bf 1 24m bgl - ge1 main: 256 kbyte work: 32 kbyte 32 kbyte datasheet 94 mb9b120m_ds706-00050-3v0-e, march 10, 2015 confidential ? package dimensions 80-pin plastic lqfp lead pitch 0.50 mm package width package length 12.00 mm 12.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.47 g 80-pin plastic lqfp (fpt-80p-m37) (fpt-80p-m37) 2009-2010 fujitsu semiconductor limited f80037s-c-1-2 120 40 21 60 41 80 61 index *12.00 0.10(.472 .004)sq 14.00 0.20(.551 .008)sq 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" (stand off) details of "a" part (.004 .002) 0.10 0.05 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) 0.50 0.20 (mounting height) .059 ?.004 +.008 ?0.10 +0.20 1.50 0~8 c dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. datasheet march 10, 2015, mb9b120m_ds706-00050-3v0-e 95 confidential 80-pin plastic lqfp lead pitch 0.65 mm package width package length 14.00 mm 14.00 mm lead shape gullwing sealing method plastic mold mounting height 1.60 mm max. code (reference) p-lqfp80-14 14-0.65 80-pin plastic lqfp (fpt-80p-m40) (fpt-80p-m40) 0.320.06 (.013.002) m 0.13(.005) 14.000.10(.551.004)sq 16.000.20(.630.008)sq * 0.1450.055 (.006.002) 0.10(.004) 0.600.15 (.024.006) 1.500.10 (.059.004) 0 ? ~7 ? 0.25(.010) 0.100.05 (.004.002) index details of "a" part 0.65(.026) 0.500.20 (.020.008) 1 20 40 21 60 41 80 61 c 2012 fujitsu semiconductor limited hmbf80-40sc-1-1 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. datasheet 96 mb9b120m_ds706-00050-3v0-e, march 10, 2015 confidential 64-pin plastic lqfp lead pitch 0.50 mm package width package length 10.00 mm 10.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.32 g 64-pin plastic lqfp (fpt-64p-m38) (fpt-64p-m38) "a" 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) m 0.220.05 0.50(.020) 12.000.20(.472.008)sq *10.000.10(.394.004)sq index 49 64 33 48 17 32 16 1 2010 fujitsu semiconductor limited f64038s-c-1-2 (stand off) details of "a" part 0.10 0.10 (.004.004) 0.60 0.15 0.25(.010) c 0.500.20 (.020.008) (mounting height) .059 ?.004 +.008 ?0.10 +0.20 1.50 0~8 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. (.009.002) (.024.006) datasheet march 10, 2015, mb9b120m_ds706-00050-3v0-e 97 confidential 64-pin plastic lqfp lead pitch 0.65 mm package width package length 12.00 mm 12.00 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.47 g 64-pin plastic lqfp (fpt-64p-m39) (fpt-64p-m39) "a" 0.10(.004) 0 . 1 4 5 0 . 0 5 5 ( . 0 0 6 . 0 0 2 ) 0.13(.005) m 0.320.05 0.65(.026) 14.000.20(.551.008)sq 12.000.10(.472.004)sq index 49 64 33 48 17 32 16 1 2010-2011 fujitsu semiconductor limited hmbf64-39sc-2-2 details of "a" part 0.100.10 0.600.15 (.024.006) 0.25(.010)bsc c .059 ?.004 +.008 ?0.10 +0.20 1.50 0~8 ? 0.500.20 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. (.013.002) (.020.008) (.004.004) datasheet 98 mb9b120m_ds706-00050-3v0-e, march 10, 2015 confidential 64-pin plastic qfn lead pitch 0.50 mm package width package length 9.00 mm 9.00 mm sealing method plastic mold mounting height 0.90 mm max weight - 64-pin plastic qfn (lcc-64p-m24) (lcc-64p-m24) c 2011 fujitsu semiconductor limited hmbc64-24sc-2-1 (.354.004) 9.000.10 (.236.004) 6.000.10 (.236.004) 6.000.10 (.354.004) 9.000.10 0.400.05 (.016.002) 0.50 (.020) (typ) 0.250.05 (.010.002) 0.45 (.018) 1pin id (0.20r (.008r)) 0.05 (.002) max (0.20 (.008)) 0.850.05 (.033.002) index area dimensions in mm (inches). note: the values in parentheses are reference values. datasheet march 10, 2015, mb9b120m_ds706-00050-3v0-e 99 confidential 48-pin plastic lqfp lead pitch 0.50 mm package width package length 7.00 mm 7.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.17 g 48-pin plastic lqfp (fpt-48p-m49) (fpt-48p-m49) c 2010 fujitsu semiconductor limited hmbf48-49sc-1-2 24 13 36 25 48 37 index *7.00 0.10(.276 .004)sq 9.00 0.20(.354 .008)sq 0.145 0.055 (.006 .002) 0.08(.003) "a" 0 ~8 .059 ?.004 +.008 ?0.10 +0.20 1.50 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) (stand off) 0.25(.010) details of "a" part 1 12 0.08(.003) m (.008 .002) 0.22 0.05 0.50(.020) (mounting height) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. datasheet 100 mb9b120m_ds706-00050-3v0-e, march 10, 2015 confidential 48-pin plastic qfn 0.5 mm package width package length 7.00 mm 7.00 mm sealing method plastic mold mounting height 0.90 mm max weight ? 48-pin plastic qfn (lcc-48p-m73) ( lcc-48p-m73 ) c 2011 fujitsu semiconductor limited hmbc48-73sc-2-1 (.276.004) 7.000.10 (.217.004) 5.500.10 (.217.004) 5.500.10 (.276.004) 7.000.10 (.010.002) 0.250.05 0.45 (.018) 1pin id (0.20r (.008r)) (.016.002) 0.400.05 (typ) 0.50 (.020) (0.20(.008)) 0.05 (.002) max (.033.002) 0.850.05 index area dimensions in mm (inches). note: the values in parentheses are reference values. lead pitch datasheet march 10, 2015, mb9b120m_ds706-00050-3v0-e 101 confidential 96-pin plastic fbga lead pitch 0.5 mm package width package length 6.00 mm 6.00 mm lead shape ball sealing method plastic mold 1.30 mm max mounting height weight 0.08 g 96-pin plastic fbga (bga-96p-m07) (bga-96p-m07) ha b c d e f g j k l 1 2 4 3 5 7 6 9 8 10 11 c 2012 fujitsu semiconductor limited b96007s-c-1-1 6.000.10(.236.004) 0.50 typ 0.20(.008) b s 0.20(.008) a s 6.000.10 (.236.004) (index area) 0.08(.003) s (.045.006) s 1.150.15 index m s a ?0.05(.002) 0.50(.020) typ a b 5.00(.197) ref 5.00(.197) ref (seated height) (.010.004) 0.250.10 (stand off) (.020) (96-?.012.004) 96-?0.300.10 b dimensions in mm (inches). note: the values in parentheses are reference values. d a t a s h e e t 102 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential ? major changes page section change results revision 1.0 - - preliminary data sheet 3 ? features ? a/d converter (max 26channels ) revised the conversion time : 1.0 s 0.8 s 5 ? uniqueid ? added the " unique id " . 6 ? product lineup ? function ? added the " unique id " . 15 to 17 ? list of pin functions ? list of pin numbers ? ? correc ted the i/o circuit type. ? corrected the pin state type. 32 ? list of pin functions ? corrected the pin function. 38 ? i/o circuit type ? added the " type : l " . 45 ? block diagram ? corrected the figure. - tioa: input input/output - tiob: output input 54 ? electrical characteristics 1. absolute maximum ratings revised the value of " tbd " . 55 2. recommended operating conditions revised the condition of " operating temperature " . 56, 57 3. dc characteristics (1) current rating ? revised the value of " tbd " . ? added " flash memory write/erase current " . 60 4. ac characteristics (3) built - in cr oscillation characteristics ? revised the condition . ? revised the footnote. 61 (4 - 2) operating conditions of main pll (in the case of using built - in high - speed cr for inp ut clock of main pll) revised the value of " tbd " . 77 5. 12 - bit a/d converter ? electrical characteristics for the a/d converter ? deleted " (preliminary value ) " . ? revised the conversion time . min: 1.0 s 0.8 s ? revised the value of " compare clock cycle ( av cc 4.5v ) " . min: 50ns 40ns ? revised the footnote. 80 6. 10 - bit d/a converter deleted " (preliminary value ) " . 81 7 . low - voltage detection characteristics revised the value of " tbd " . 82 8 . mainflash memory write/erase characteristics ? revised the value of " tbd " . ? revised the value of " sector erase time " . - large sector typ: 1.065s 1.1s - small sector typ: 0.606s 0.3s ? revised the value of " chip erase time " . typ: 9.11s 6.8s ? deleted " ( targeted value ) " . revision 1.1 - - company name and layout design change revision 2.0 2 ? features ? on - chip memories [flash memory] revised the features of dual operation flash memory ? multi - function serial interface [i 2 c] ? corrected the mo de. high speed mode fast mode 3 ? general - purpose i/o port revised the features of 5v tolerant i/o. 4 ? multi - function timer corrected the number of a/d activating compare channels. 3ch. 2ch. 6 ? product lineup ? function ? corrected the number o f a/d activating compare channels. 3ch. 2ch. ? revised built - in cr. high - speed: 4mhz ( 2%) 4mhz low - speed: 100khz(typ) 100khz 7 revised the footnote. 20 ? list of pin functions ? list of pin numbers corrected the pin number of zin1_1. 23 ? l ist of pin functions corrected the pin number of adtg_2. 28 corrected pin numbers of sin0_1 and sot0_1. 30 corrected the pin number of dtti0x_2. 36 ? i/o circuit type type h : revised the value of " tbd " . d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3 v0 - e 103 confidential page section change results 43 ? handling devi ces ? sub crystal oscillator ? added the descriptions . 46 ? block diagram ? corrected the figure. - a/d activation compare: 3ch 2ch 48 ? memory map ? memory map (2) ? added the explanatory note. 53 ? pin status i n each cpu state ? list of pin status ? added the pin function of selected analog output about type l. 54 ? corrected the footnote. s ub cr timer low - speed cr tim 56 ? electrical characteristics 2. recommended operating conditions ? ? added the note and f ootnote. ? corrected the value of analog referen ce voltage avrh . min.: avss 2.7 57 3. dc characteristics (1) current rating ? ? added notes and footnotes. ? added the remarks of icc. ? added the frequency of main clock crystal oscillator in remarks. 61 4. ac characteristics (2) sub clock input cha r acteristics added the footnote . 62 (3) built - in cr oscillation characteristics ? built - in high - speed cr ? added " frequency stabilization time " ? added notes and footnotes. 64 (6) power - on reset timing ? ? ad ded " timing until releaseing power - on reset " ? a dded the timing chart 66 (8) csio timing ? corrected the title. uart timing csio timing ? corrected the notefoot. uart multi - function serial 68,70,72 corrected the notefoot. uart multi - function serial 77 (11) i 2 c timing ? ? revised the condition . ? revised the footnote. 79 5. 12 - bit a/d converter ? electrical character istics for the a/d converter ? ? changed the name of parameter. ? non linearity error integral nonlinearity ? differential linearity error differential nonlinearity ? changed the symbol. o f zero transition voltage. vo t v zt ? changed the pin name. an 00 to an26 anxx ? corrected the value of v 0t, v fst, ts, tstt , and reference voltage. ? revides footnotes. 80 change the figure. an00 to an26 anxx 81 ? difinition of 12 - bit a/d converter terms ? ? linearity error integral nonlinearity ? differential linearity error differential nonlinearity ? v 0t v zt 82 6. 10 - bit d/a converter ? electrical characteristics for the d / a c onverter ? ? revised the remark of idda. d/a operation d/a 1unit operation ? changed the name of parameter. ? linearity error int egral nonlinearity ? differential linearity error differential nonlinearity 83 7. low - voltage detection characteristics (1) low - voltage detection reset ? ? corrected the condition and the value. ? added the note and the footnote. ? added lvd detection del ay time . 84 (2) interrupt of low - voltage detection ? ? corrected the condition and the value. ? added lvd detection delay time . 85 8. flash memory write/erase characteristics ? changed the title of chapter. main flash memory write/erase characteristics flash memory write/erase characteristics 86 9. return time low - power consumption mode ? added the chapter return time from low - power consumption mode . revision 3.0 2 ? features ? usb interface added the description of pll for usb 3 5 , 3 6 ? i/o circuit type added about +b input 4 8 ? memory map memory map(2) added the summary of flash memory sector and the note 52 ? pin status in each cpu stae list of pin status ? changed the pin status of i - type 5 5 , 5 6 ? electrical characteristics 1. absolute maximum r atings added the clamp maximum current added about +b input 5 8 - 6 0 ? electrical characteristics 3. dc characteristics (1) current rating changed the table format added main timer mode current moved a/d converter current moved d/a converter curre nt d a t a s h e e t 104 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential 6 5 ? electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main pll (4 - 2) operating conditions of main pll added the figure of main pll connection 6 8 - 7 5 ? electrical characteristics 4. ac characteristics (7) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 7 6 ? electrical characteristics 4. ac characteristics (9) external input timing ? added in put pulse width of wkupx pin 8 1 ? electrical characteristics 5. 12bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage added conversion time at avcc < 4 .5v 9 2 , 9 3 ? ordering information change to full part number d a t a s h e e t march 1 8 , 201 5 , mb9b120m_ds706 - 00050 - 3 v0 - e 105 confidential d a t a s h e e t 106 mb9b120m_ds706 - 00050 - 3v0 - e, march 1 8 , 201 5 confidential colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including without li mitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, cou ld have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffi c control, mass transport control, medic al life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party fo r any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measure s into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those pr oducts. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any p roduct without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non - infringement of third - party rights, or a ny other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 201 2 - 201 5 spansion all rights reserved. spansion ? , the spansion log o, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. |
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